1. Field of the Invention
The present invention relates to a phase-locked loop circuit, and more particularly to a phase-locked loop circuit implemented as a digital circuit.
2. Description of the Prior Art
Phase-locked loop (PLL) circuits have heretofore been based on the analog circuit technology. In a widespread PLL design, an oscillated clock signal is fed back to a phase comparator, and an analog oscillating circuit is controlled based on the result of comparison between the clock signal which is fed back and an input clock signal.
According to a recent attempt to realize a digital PLL, an oscillating circuit comprises a ring oscillator composed of an odd number of series-connected inverters as disclosed, for example, in Japanese Utility Model Laid-Open No. 13025/87. However, the disclosed oscillating circuit is not of the fully digital type because an NMOS threshold voltage is controlled in an analog manner to control the delay times of the inverters for controlling the oscillation frequency.
In recent years, CMOS digital LSI circuits have been finding wide industrial use. Great advantages can be achieved if a circuit such as a PLL, which has heretofore been implemented as an analog circuit, can be realized by a CMOS digital LSI circuit.
One solution for realizing a PLL with a CMOS digital LSI circuit is to use a ring oscillator. However, since the delay times of inverters which determine the oscillation frequency of the ring oscillator vary from LSI sample to LSI sample by a magnitude ranging from about 1/2 to 2 times, it is necessary to introduce some digital arrangement for synchronizing the oscillation frequency of the ring oscillator with the frequency of the input signal. The delay times of inverters on one LSI chip vary somewhat from each other.